In the past, integrated circuits, including those employing Complementary Metal Oxide Silicon (CMOS) logic, have been tested by applying one or more strings of binary values (vectors) to the input(s) of the integrated circuit over time and then observing the response to each applied vector. By comparing each observed response to the corresponding response expected for a fault-free integrated circuit, faults in the circuit can be detected. The degree to which the faults in an integrated circuit manifest themselves, usually described in terms of fault coverage, is dependent on the size of the vector set applied to the integrated circuit.
Another technique for testing a CMOS integrated circuit is to measure the current (I.sub.DDQ) during the interval when the integrated circuit is operating in its quiescent state. A fault-free CMOS integrated circuit draws no current in its quiescent state, whereas a defective CMOS device typically draws a small amount of drain (source) current. A distinct advantage of testing a CMOS device by measuring its quiescent current I.sub.DDQ is that the number of vectors required to achieve a certain level of fault coverage is much smaller as compared to conventional testing techniques.
To date, implementation of I.sub.DDQ testing has been hindered by the need for special purpose testing equipment external to the integrated circuit being tested. Another factor hindering implementation of I.sub.DDQ testing has been the need carry out such testing at a much slower rate than conventional testing because of testing speed restrictions imposed by the manner in which such equipment must be coupled to the integrated circuit(s) under test.
Thus, there is need for a technique for carrying out I.sub.DDQ testing which overcomes the aforementioned disadvantages.